Staff VLSI Design Engineering (SOC Verification, System Verilog, UVM)with 8 to 12 years of experience

About this role

Job Description We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success. Key Responsibilities: Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP …