Sr. Principal Program Manager, ASIC Post-Silicon Engineering

About this role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is seeking a <span data-teams="true">S<strong>r. Principal Program Manager, ASIC Post-Silicon Engineering</strong> </span>to lead execution of complex post-silicon programs for AI connectivity products. This role owns cross-functional program delivery from silicon power-on through bring-up, validation, qualification, customer sampling, and release to manufacturing - RTM, aligning engineering execution with product, customer, and business milestones.</p> <p>The ideal candidate brings deep experience leading technically complex semiconductor or systems programs involving silicon, firmware, software, platform, validation, manufacturing, and customer readiness. They are highly effective at driving cross-functional alignment, managing program risk, and communicating crisply with both engineering teams and executive stakeholders.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li class="text-start "> <p><strong>Program Ownership and Execution</strong></p> <ul> <li class="text-start ">Own the integrated post-silicon program plan from silicon power-on through bring-up, validation, qualification, customer sampling, and RTM, ensuring alignment across silicon, firmware/software, platform, compliance, production test and manufacturing milestones.</li> <li class="text-start ">Drive program schedules, budgets, resources, interdependencies, and risk management, balancing scope, schedule, and cost trade-offs while maintaining clear communication with executives and key stakeholders.</li> <li class="text-start ">Drive validation readiness and execution alignment for high-speed connectivity products, including validation plan coverage, firmware and hardware readiness, test content, platform availability, and milestone tracking for technologies such as PCIe, Ethernet, SerDes, and platform-level interconnect solutions.</li> <li class="text-start ">Manage phase-gate exit criteria, readiness checkpoints, dashboards, and decision forums to support predictable delivery and rapid cross-functional decision-making.</li> </ul> </li> <li class="text-start "> <p><strong>Stakeholder Management and Cross-Functional Leadership</strong></p> <ul> <li class="text-start ">Lead cross-functional execution across engineering, product, operations, quality, manufacturing, and customer-facing teams.</li> <li class="text-start ">Drive internal technical issue resolution through structured triage, escalation management, milestone reviews, and executive reporting; surface risks early, drive accountability, and enable timely decisions and recovery plans.</li> <li class="text-start ">Align priorities, trade-offs, readiness criteria, and launch decisions with business and customer goals across stakeholders.</li> </ul> </li> <li class="text-start "> <p><strong>Customer Sampling and Release to Manufacturing</strong></p> <ul> <li class="text-start ">Own customer sampling readiness, including sample allocation, validation exit criteria, firmware/software readiness, known-issue documentation, errata, release notes, reference platforms, and validation summaries.</li> <li class="text-start ">Drive customer-facing issue resolution and escalation management in partnership with product management, applications engineering, sales, quality, and engineering teams, ensuring materials and support plans are aligned with deployment.</li> <li class="text-start ">Lead cross-functional execution from engineering validation through RTM phase-gate exit.</li> <li class="text-start ">Partner with product engineering, test engineering, operations, manufacturing, supply chain, and quality teams to drive manufacturing readiness reviews, production ramp execution, and production-release approvals, including ATE readiness, characterization, yield learning, failure analysis, reliability qualification, waivers, and errata.</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li class="text-start ">10+ years of experience in semiconductor engineering, post-silicon validation, system validation, silicon bring-up, product…