Sr. Principal Program Manager, ASIC Design

About this role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>As a <strong>Sr. Principal Program Manager, ASIC Design</strong> at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.</p> <p>You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.</p> <p>This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li class="text-start "> <p><strong>Program Execution & Planning</strong></p> <ul> <li class="text-start ">Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.</li> <li class="text-start ">Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.</li> <li class="text-start ">Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.</li> </ul> </li> <li class="text-start "> <p><strong>Cross-Functional Alignment & Coordination</strong></p> <ul> <li class="text-start ">Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.</li> <li class="text-start ">Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.</li> <li class="text-start ">Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.</li> </ul> </li> <li class="text-start "> <p><strong>Risk Management & Decision-Making</strong></p> <ul> <li class="text-start ">Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.</li> <li class="text-start ">Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.</li> </ul> </li> <li class="text-start "> <p><strong>Process & Operational Excellence</strong></p> <ul> <li class="text-start ">Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li class="text-start ">Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.</li> <li class="text-start ">10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.</li> <li class="text-start ">Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.</li> <li class="text-start ">Experience with advanced process nodes and high-performance ASIC/SoC development.</li> <li class="text-start ">Strong understanding of ASIC development milestones from product requirements through final GDS handoff.</li> <li class="text-start ">Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.</li> <li class="text-start…