Sr. Director - SoC Front End Engineering

About this role

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

This role will be on-site 5 days a week in NW Austin.

Ambiq is seeking a Senior Director of Front-End Engineering to lead the design and implementation of our Edge AI MCU portfolio — driving the digital design, integration, and verification of ultra-low-power SoCs purpose-built for machine learning at the edge.

This is a hands-on, strategic leadership role responsible for building and scaling a world-class engineering organization that delivers breakthrough performance-per-microwatt. The ideal candidate combines deep technical acumen with people leadership excellence and has a proven record of bringing advanced SoCs from architecture to production.

Key Responsibilities

Technical Leadership

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Own and drive the front-end design of Ambiq’s Edge AI MCU platforms — including CPU subsystems, neural accelerators, security, memory, and peripheral integration.

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Lead architecture definition, RTL design, and subsystem integration focused on power-optimized AI compute and real-time performance.

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Develop and enforce world-class design methodologies across RTL, verification (UVM), and static checks (lint, CDC, DFT readiness).

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Partner with Architecture and Physical Design teams to ensure seamless PPA optimization and first-silicon success.

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Evaluate and deploy next-generation EDA tools, design automation, and verification infrastructure to accelerate tapeout readiness.

Execution & Delivery

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Drive design execution for multiple MCU programs concurrently, from concept through production tapeout.

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Define and track program milestones, deliverables, and risk management plans with cross-functional stakeholders.