SerDes Lead Designer
Celerocommunicationsinc · Irvine, CA, San Jose, CA · 2026-06-18
About this role
About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI.
Preferred Location: Irvine, CA
Alternate Locations: San Jose, CA | Vancouver, BC Canada | Ottawa, ON, Canada
Candidate will have the opportunity to architect and design SerDes for next generation transceivers.
What You Will Do:
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
Skills asked for
- matlab
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