Senior Principal Technologist – Memory
Asteralabs · San Jose, California, United States · 2026-07-02
About this role
<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p><span data-contrast="none">Are you&nbsp;passionate about pushing the boundaries of&nbsp;system,&nbsp;memory,&nbsp;software,&nbsp;and&nbsp;chip&nbsp;architecture? Do you&nbsp;thrive when&nbsp;pitching&nbsp;cutting-edge technology solutions to&nbsp;customers&nbsp;and&nbsp;industry&nbsp;partners? We are seeking&nbsp;a creative customer facing&nbsp;Technologist&nbsp;to help facilitate&nbsp;Astera’s development&nbsp;of&nbsp;data center&nbsp;memory&nbsp;solutions.&nbsp;In this role, you will play a pivotal role in driving the&nbsp;architecture and definition&nbsp;of future products by leveraging your expertise in&nbsp;system architecture,&nbsp;SOC&nbsp;memory sub-system&nbsp;architecture, PCIe/CXL&nbsp;technologies,&nbsp;DRAM/memory architecture,&nbsp;and&nbsp;hardware-software&nbsp;co-design. You will have the opportunity to directly engage with customers,&nbsp;influence product features and roadmap,&nbsp;and help drive innovation to better solve our&nbsp;customers’&nbsp;bottlenecks in hyperscale data centers.</span><span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:2,&quot;335559740&quot;:300}">&nbsp;</span></p> <p><strong><span data-contrast="none">This role is fully in person, in&nbsp;San Jose.&nbsp;Some travel may be required.</span></strong><span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:2,&quot;335559740&quot;:300}">&nbsp;</span></p> <p><strong><span data-contrast="none">Basic qualifications</span></strong><span data-contrast="none"> </span> </p> <ul> <li><span data-contrast="none">BS in Electrical or computer engineering, MS or PhD preferred. </span><span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:2,&quot;335559740&quot;:300}">&nbsp;</span></li> <li><span data-contrast="none">≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers&nbsp;</span> </li> <li>Deep experience with PCIe 5/6, and CXL including protocol level depth&nbsp; </li> <li>Expertise in OS software integration including memory allocation/management </li> <li>Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc) </li> <li>Deep expertise and understanding of memory components (DRAM, etc) </li> <li>Strong understanding of datacenter system architecture and design challenges </li> <li>Strong understanding of “full stack” solutions from silicon to application integration </li> <li>Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases </li> <li>Ability to dig deeply into technical challenges and use cases&nbsp; </li> <li>Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. </li> <li>Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment. </li> <li>Willingness to travel occasionally for customer meetings and industry events.<span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:2,&quot;335559740&quot;:300}">&nbsp;</span></li> </ul> <p><strong><span data-contrast="none">Preferred experience</span></strong><span data-contrast="none"> </span><span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:2,&quot;335559740&quot;:300}">&nbsp;</span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3"…
Similar jobs
- Senior/Principal Physical Design EngineerCelerocommunicationsinc · San Jose
- Senior/Principal Full-Chip Physical Verification EngineerCelerocommunicationsinc · San Jose
- Senior Principal System Validation EngineerAsteralabs · San Jose
- Senior Principal Product Manager - CosmosAsteralabs · San Jose
- Senior Principal Engineering Program ManagerAsteralabs · San Jose
- Senior Principal Digital Design EngineerAsteralabs · San Jose
Your next role is already in here.
Search live openings from thousands of employers, save the ones worth a second look, and let JobBob keep watch for the rest.