Senior FPGA Engineer

About this role

<p> </p> <h2><strong><span data-contrast="auto">About Epirus </span></strong><span data-ccp-props="{}"> </span></h2> <p><span class="NormalTextRun CommentStart CommentHighlightPipeRestV2 CommentHighlightRest SCXW6194141 BCX8">E</span><span class="NormalTextRun CommentHighlightPipeRestV2 SCXW6194141 BCX8">pirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.</span></p> <p><strong><span data-contrast="auto">Job objective: </span></strong><span data-contrast="auto"><span class="TextRun SCXW124030239 BCX0" lang="EN" data-contrast="none"><span class="NormalTextRun SCXW124030239 BCX0">This is an exciting role an innovative, high-growth defense technology company. </span></span><span class="TextRun SCXW124030239 BCX0" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW124030239 BCX0">The ideal candidate for the position is someone who has experience designing, verifying, and integrating </span><span class="NormalTextRun SCXW124030239 BCX0">state-of-the-art</span><span class="NormalTextRun SCXW124030239 BCX0"> FPGA systems and embedded processing solutions for RF applications. </span><span class="NormalTextRun SCXW124030239 BCX0">As a </span><span class="NormalTextRun CommentStart SCXW124030239 BCX0">Sr.</span><span class="NormalTextRun SCXW124030239 BCX0"> FPGA Engineer</span><span class="NormalTextRun SCXW124030239 BCX0">, you will work closely with a talented, multi-disciplinary engineering team in a fast-paced environment to apply emerging technologies in innovative ways to rapidly produce new products</span><span class="NormalTextRun SCXW124030239 BCX0">.  </span><span class="NormalTextRun SCXW124030239 BCX0">  </span></span></span><span class="EOP SCXW124030239 BCX0" data-ccp-props="{}"> </span></p> <h2><strong><span data-contrast="auto">Duties </span></strong><span data-ccp-props="{}"> </span></h2> <ul> <li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Design and verification of RTL modules for FPGA applications</span></li> <li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Ownership of entire FPGA designs from initial architecture trades through implementation, verification, and hardware bringup, including FPGA sizing estimation and IO planning.</li> <li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Lead initial testing and bring-up of custom FPGA circuit cards, validating functionality of on-board peripherals including memory interfaces, Ethernet controllers, and integrated sensors.</li> <li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Automating test environment (up to and including hardware-in-the-loop testing), lab equipment, and measurement devices</li> <li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Capturing design tradeoffs, state machine flow, system address maps, and block…