Senior Design Verification Engineer

About this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for a Senior Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic Qalifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
required, and a Maser’s is preferred.

• ≥2 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
Networking applications.

• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
customer meetings in advance, and to work with minimal guidance and supervision.

• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

• Authorized to work in Canada and start immediately.

Required Experience:

• Experience with integrating C/C++ in System Verilog environments using DPI/PLI

• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.

• Experience in developing infrastructure and tests in a hybrid directed and constrained…