Process Integration Engineer

About this role

Job Title: R&D Engineer - Process Integration

Location: Covington, GA

Job Type: Full-Time

About Us: Absolics is a leading provider of advanced packaging technologies and services, offering scalable solutions for businesses of high-performance computing. We offer smart, innovative services to dozens of clients globally. By dedicating our efforts to establishing large glass substrates with built-in active and passive elements, our goal is to provide significant improvement in signaling characteristics and power consumption compared to existing solutions.

Job Description:

We are seeking a highly skilled and experienced Process Integration Engineer to join our team. The successful candidate will be responsible for orchestrating and integrating critical process steps, such as:

• dielectric materials selection and application

• lithography

• wet + dry clean/etch/develop processes

• PVD and electroplating

into a coherent, manufacturable process flow for fine-pitch, next-generation packaging architectures. You will support finalizing various Process Integration Plans, defining design rules, managing process window tradeoffs across module boundaries, and be the primary technical decision-maker to help navigate constraints in the full process flow. You will work daily with the lithography, wet/dry process, dielectric, and plating engineers, translating their individual process capabilities into a working end-to-end flow, while also engaging with device/package design teams on architectures feasibility. In an early-stage environment, this role carries enormous influence on the finalized architecture and build-up decisions.

Key Responsibilities:

• Oversee process integration, manage scheduling, and provide comprehensive progress reports to upper management.

• Develop and implement process integration strategies to optimize production yield and efficiency.

• Coordinate with cross-functional teams to ensure seamless integration of processes.

• Monitor and analyze process performance, identifying areas for improvement.

• Ensure compliance with industry standards and safety regulations.

• Troubleshoot and resolve process-related issues in a timely manner.

• Maintain detailed documentation of processes and procedures.

• Generate innovative ideas for patent filings.

Required Skills:

• Demonstrated experience integrating multi-step package build up process flows (SAP and/or damascene), from lithography through metallization and dielectric build-up

• Strong working knowledge across the full unit-process stack: photolithography, wet/dry etch, PVD seed deposition, dielectric film processing, and electroplating, sufficient to identify cross-process interactions and failure handoffs

• Experience authoring or owning Process Integration Plans, design rules (line/space, via CD, registration/overlay budgets, taper angle specs), and process flow documentation

• Track record of root-causing yield or reliability excursions that span multiple process modules (e.g., seed undercut driving downstream plating defects, via CD variation driving lithography-etch mismatch)

• Statistical process control and DOE methodology for multi-variable, multi-step process optimization

• Strong cross-functional collaboration skills; ability to translate unit-process engineer findings into integration-level decisions and vice versa

• Familiarity with metrology and failure analysis techniques across the flow (SEM, FIB cross-section, CD-SEM, overlay metrology, electrical test)

• Understanding of registration, overlay, and CD budget allocation across sequential build-up layers

• Fluent in English; proficiency in Korean is a plus.

Preferred Skills

• Experience with glass core substrates

• Direct experience scaling fine line/space RDL, including via CD control and multi-layer registration challenges

• Experience with any next-gen architecture enablement: glass core/glass interposer integration, panel-level processing, co-packaged optics, hybrid bonding, or fan-out heterogeneous integration

• Familiarity with bifurcated roadmap considerations (high-performance AI/HPC vs. cost-optimized mainstream paths) and how that shapes architecture and material tradeoffs

• Experience building DFM (design-for-manufacturing) guidelines in collaboration with package design teams

• Knowledge of reliability qualification frameworks (JEDEC, IPC) as they constrain integration choices

• Familiarity with new equipment or process technology evaluation and incorporation into an existing flow (e.g., panel-level CMP, advanced laser/plasma drill, novel dielectric chemistries)

• Experience presenting integration roadmaps or technical reviews to leadership or cross-functional…