Principal Physical Design Engineer

About this role

<p>Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.</p> <p>We are seeking an experienced <strong>Principal Physical Design Engineer</strong> to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.</p> <p><strong>Locations</strong>: San Jose, CA and Irvine, CA </p> <p><strong>Core Responsibilities</strong><br>• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.<br>• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.<br>• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers<br>• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.<br>• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.<br>• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness. </p> <p><strong>Key Qualifications</strong><br>• Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).<br>• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).<br>• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).<br>• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.</p> <p><em>Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)</em></p>