PLL Design Engineer

About this role

<p><strong><span data-contrast="auto">About the job</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">Are you a </span><strong><span data-contrast="auto">PLL Design Engineer, </span></strong><span data-contrast="auto">who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a </span><strong><span data-contrast="auto">High-Speed CMOS PLL Analog Design Engineer </span></strong><span data-contrast="auto">–who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto"><strong>Preferred Locations</strong>: Irvine, CA and </span><span data-contrast="auto">San Jose, CA</span></p> <p><span data-ccp-props="{}"><strong>Alternate Locations</strong>: Vancouver, BC and Ottawa, ON</span></p> <p><span data-contrast="auto">Candidate will have the opportunity to </span><strong><span data-contrast="auto">architect and design PLLs </span></strong><span data-contrast="auto">for next generation transceivers.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">What You Will Do:</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="10" data-aria-level="1"><span data-contrast="auto">Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="11" data-aria-level="1"><span data-contrast="auto">Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="12" data-aria-level="1"><span data-contrast="auto">Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto">Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies</span><span…