Manager, Package Design Engineering

About this role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products.</p> <p>As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.</p> <p>This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Team Leadership & Execution <ul> <li>Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows</li> <li>Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs</li> <li>Lead design reviews, audits, and issue resolution through bring-up and production ramp</li> </ul> </li> </ul> <ul> <li>Package Design Delivery <ul> <li>Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production</li> <li>Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements</li> <li>Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery</li> </ul> </li> </ul> <ul> <li>Cross-Functional Collaboration <ul> <li>Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges</li> <li>Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps</li> <li>Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms</li> </ul> </li> </ul> <ul> <li>Methodology & Automation <ul> <li>Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li>Bachelor's degree in Electrical Engineering, Materials Science, or related field</li> <li>10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP</li> <li>5+ years of leadership experience managing teams or technical organizations in IC packaging environments</li> <li>Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool</li> <li>Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)</li> <li>Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals</li> <li>Proven experience working with OSATs and substrate vendors through development and production ramp</li> <li>Experience working with OSATs and substrate vendors through development and production ramp</li> <li>Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration</li> </ul> <p><strong>Preferred Qualifications</strong></p> <ul> <li>Master's…