Lead Product Engineer

About this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a Tech Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production.

As a key technical contributor, you will own the RF and signal integrity aspects of product engineering — from silicon characterization and validation through production test development and customer-facing debug. You'll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution.

With Astera Labs' portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance, you'll tackle some of the most demanding RF and physical layer challenges in the semiconductor industry.

Key Responsibilities

•
Silicon Characterization & Validation

• Lead RF and signal integrity characterization of high-speed SerDes across PCIe Gen 6/7, Ethernet, and UALink/UCI interfaces

• Perform bench measurements using high-speed oscilloscopes, VNAs, BERTs, and TDRs to validate silicon performance against specifications

• Analyze S-parameters, eye diagrams, jitter, and channel loss to characterize physical layer performance across PVT corners

• Drive silicon qualification and reliability testing to ensure products meet production readiness criteria

•
Production Test Development

• Develop and optimize ATE test programs for RF and high-speed I/O parametric testing

• Define test coverage strategies that balance quality, cost, and throughput for volume manufacturing

• Correlate bench characterization results with ATE measurements to ensure production screening effectiveness

• Partner with OSAT and test vendors to bring up and qualify production test hardware and loadboards

•
Customer Debug & Applications Support

• Provide RF and physical layer expertise to support customer platform bring-up and debug activities

• Analyze field returns and customer escalations related to signal integrity and link performance issues

• Develop reference measurement methodologies and application notes for high-speed interfaces

• Collaborate with applications engineering to resolve interoperability challenges across diverse customer platforms

•
Cross-Functional Engineering Collaboration

• Partner with silicon design teams to provide characterization feedback that informs next-generation product improvements

• Drive DFT and design-for-manufacturing improvements based on production test learnings

• Contribute to product specifications and datasheet development with measured silicon performance data

Basic…