Director, Physical Design

About this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Director, Physical Design

Location: Hyderabad, India

About Astera Labs

Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor products power the world's leading cloud service providers, hyperscalers, and server OEMs. As we scale our next-generation ASIC programs, we are building a world-class Physical Design team in Hyderabad to drive silicon success from RTL to GDSII.

Role Overview

Astera Labs is seeking a Director, Physical Design to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.

The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.

Key Responsibilities

Leadership & Team Building

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology functions

• Define team structure, hiring roadmap, and career development paths for PD engineers

• Foster a culture of technical excellence, ownership, and continuous improvement

• Partner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities

Physical Design Execution

• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII signoff

• Drive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (DRC/LVS)

• Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and below)

• Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability targets

• Manage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPA targets

Methodology & CAD

• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass success

• Evaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)

• Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design quality

• Collaborate with EDA vendors on tool evaluation, adoption, and methodology improvements

Cross-Functional Collaboration

• Partner closely with RTL, DV, DFT, packaging, and architecture teams to enable seamless integration of complex subsystems (SerDes, high-speed PHYs, die-to-die interfaces, etc.)

• Provide physical design input during architecture and floorplan feasibility studies, die sizing, and IP evaluation

• Represent the Hyderabad PD team in global design reviews, tapeout readiness reviews, and leadership forums

Basic Qualifications

• Bachelor's or master’s degree in electrical engineering, Electronics, or Computer Science

• 18+ years of experience in ASIC physical design, with at least 5 years in a leadership or management role

• Should be hands on with a proven track record of multiple successful tapeouts at advanced nodes (7nm or below); experience at 5nm/3nm strongly preferred

• Deep hands-on expertise in full-chip physical design: floorplanning,…