Chip Lead, Senior Director

About this role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><span data-contrast="auto">Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.</span><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}"> </span></p> <p><span data-contrast="auto">As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers.</span><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}"> </span></p> <p><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}">Location - San Jose, CA OR Israel </span></p> <p><strong><span data-contrast="auto">Key Responsibilities</span></strong><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="auto">Product Technical Ownership</span></strong><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto">Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement</span><span data-ccp-props="{"134233279":true,"201341983":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto">Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met</span><span…