Analog Design Engineer

About this role

<p><strong><span data-contrast="auto">About the job</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">Are you an </span><strong><span data-contrast="auto">Analog Design Engineer, </span></strong><span data-contrast="auto">who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology powering next generation AI? We are looking for an </span><strong><span data-contrast="auto">Analog Design Engineer </span></strong><span data-contrast="auto">– someone who is excited to join a fast-growing Start-Up Company growing a group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto"><strong>Preferred Location</strong>: </span><span data-contrast="auto">Irvine, CA</span></p> <p><span data-ccp-props="{}"><strong>Alternate Locations</strong>: San Jose, CA | Vancouver, BC | Ottawa, ON</span></p> <p><span data-contrast="auto">Candidate will have the opportunity to </span><strong><span data-contrast="auto">architect and design circuits for high performance transceivers </span></strong><span data-contrast="auto">and other critical analog functions.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">What You Will Do:</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Clock generation and distribution (VCOs, PLL, clock distribution, etc)</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc)</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">New techniques for the development of next generation optical transceiver</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2"…